The present invention relates to control circuits for the switching of inductive loads. More particularly, the present invention relates to a monolithically integratable control circuit comprising a push-pull transistor output stage which may be used to drive relays, solenoids and D.C. motors.
The simplest type of push-pull transistor output stage is formed by a pair of complementary transistors operating in class B. These transistors are inserted in series, by means of their emitter and collector terminals, between the two terminals of a supply voltage and are alternately driven to conduct, in phase opposition, by their base terminals.
This leads to opposite current flows in the load which is connected to an output terminal formed by the point of connection between the two transistors.
Since the switching of each of the transistors of the output stage does not take place instantaneously, but with a time transient whose duration is not negligible when the transistors are conducting at saturation, the simultaneous conduction of the two transistors cannot be avoided during the switching of the output stage if they are simply controlled in phase opposition.
The simultaneous conduction of the two transistors generally leads to an undesired increase in the dissipation of power in the output stage itself.
When the load connected to the output stage is of an inductive type, the counter-electromotive force induced during switching of the output stage by the current passing through it abruptly raises the collector-emitter voltage of the transistor in the cut-off phase which is still, however, conducting, thereby causing a power dissipation peak in this transistor which may in some cases have destructive effects.
For this reason, it is necessary to prevent the transistors of a push-pull output stage included in a control circuit for the switching of inductive loads from conducting simultaneously during switching. The simplest solution to this problem would be, in a control circuit with a push-pull output stage, to provide the conduction command for the output transistor which is cut off with a suitable delay with respect to the cut-off command for the transistor in conduction.
In practice, the application of this solution to a control circuit would entail the use of comparatively complex circuit means which would therefore be costly in terms of integration areas.
U.S. Pat. No. 4,612,452 issued Sept. 16, 1986, to Fabrizio Stefani et al. discloses a control circuit for the switching of inductive loads based on a different operating principle which is more viable from an industrial point of view.
This control circuit, a diagram of which is shown in FIG. 1, comprises an output stage with a bipolar PNP transistor T.sub.1 and a bipolar NPN transistor T.sub.2 whose collector terminals are connected together to form an output terminal of the circuit.
The emitter terminals of T.sub.1 and T.sub.2 are respectively connected to the positive terminal +V.sub.cc and the negative terminal -V.sub.cc of a supply voltage. The base terminal of the transistor T.sub.1 is connected to the collector terminal of a bipolar PNP transistor T.sub.3. The base terminal of the transistor T.sub.2 is connected to the collector terminal of a bipolar NPN transistor T.sub.4.
The emitter terminals of the transistors T.sub.3 and T.sub.4 are respectively connected to the positive terminal +V.sub.cc and the negative terminal -V.sub.cc.
The base terminals of the transistors T.sub.1 and T.sub.4 are respectively connected to the collector terminal and the emitter terminal of a bipolar NPN transistor T.sub.14.
The base terminals of the transistors T.sub.3 and T.sub.2 are respectively connected to the collector terminal and the emitter terminal of a bipolar NPN transistor T.sub.23.
The base terminals of the transistors T.sub.14 and T.sub.23 are connected to a circuit control means, shown by a rectangular block designated by the letter C formed, for example, by the differential structure described in the above-mentioned patent.
This circuit control means C is connected to a switching signal source shown in FIG. 1 by a block SW and in response to the switching signals generated by source SW, drive the transistors T.sub.14 and T.sub.23 to conduct alternately. Consequently, when the transistors T.sub.1 and T.sub.4 are conducting, the transistors T.sub.2 and T.sub.3 are cut off and vice versa. The transistors T.sub.1 and T.sub.2 of the output stage are driven to conduct at saturation.
In accordance with the above-mentioned patent the transistors T.sub.3 and T.sub.4 also conduct at saturation.
For understanding of the operation of the circuit it is assumed that a switching signal causes the cut-off of the transistor T.sub.14 and the conduction of the transistor T.sub.23.
The transistor T.sub.3 begins, with a negligible delay, to conduct at saturation and it extracts charges from the base of the transistor T.sub.1, thereby reducing the duration of the switching transient from saturation to the cut-off of this transistor. The transistor T.sub.4 continues, however, to conduct, initially at saturation until the charges stored in its base are depleted. During this transient, the transistor T.sub.4 continues to absorb the emitter current of the transistor T.sub.23, thereby preventing the conduction of the transistor T.sub.2 which consequently switches with a delay determined by the saturation conditions of the transistor T.sub.4.
The transistors T.sub.3 and T.sub.4, by accelerating the cut-off of the transistor T.sub.1 and delaying the conduction of the transistor T.sub.2, make it possible to prevent the simultaneous conduction of the transistors T.sub.1 and T.sub.2 or to limit its duration appropriately such that it does not harm the integrity of the device itself.
The operation of the circuit is identical and symmetrical in the opposite switching case. That is, the transistor T.sub.4 accelerates the cut-off of the transistor T.sub.2, while the transistor T.sub.3 delays the conduction of the transistor T.sub.1 thereby preventing the damaging effects of simultaneous conduction in this case as well.
The economic viability of this solution is clear from the fact that any damaging simultaneous conduction may be avoided simply by using two conventional bipolar transistors Thd 3 and T.sub.4 as additional components.
In addition, the transistors T.sub.3 and T.sub.4 do not entail any supply current absorption increase since the base current of the output transistor T.sub.1 being supplied as an output is re-used, via the transistor T.sub.14, as an input base current for the transistor T.sub.4 (less the negligible base current of the transistor T.sub.14) and the base current, being supplied as an input, of the transistor T.sub.2 is re-used, via the transistor T.sub.23, as the output base current of the transistor T.sub.3 (less the negligible base current of the transistor T.sub.23).
However, the control circuit for the switching of inductive loads described above may be subject, when embodied in practice as a monolithically integrated circuit, to a drawback which is closely linked to technological problems connected with this application.
As known to persons skilled in the art, there is a possibility of leakage currents from the transistors of an integrated circuit even when these are kept cut off. In the case in question, leakage currents from the transistor T.sub.14 and T.sub.23 may lead to undesired re-conduction of the transistor T.sub.3 and T.sub.4 with detrimental effects on the accuracy of control of the output transistors T.sub.1 and T.sub.2.